Zephan Enciso Michaels, Ph.D.

Research Interests

• Deployment of edge inference in safety-critical, SWaP-C constrained systems
• Hardware acceleration of uncertainty-aware artificial intelligence
• Novel devices, circuits, and architectures for machine learning

Education

Ph.D. Computer Science and Engineering, April 2026, University of Notre Dame

• Tactical Edge: Accelerating Trusted, Autonomous AI for Safety-Critical, Resource-Constrained Systems
• Advisors: Prof. Michael Niemier & Prof. Ningyuan Cao
• Committee: Prof. Xiaobo (Sharon) Hu, Prof. Kai Ni, and Prof. Yiyu Shi

M.S. Computer Science and Engineering, May 2025, University of Notre Dame

B.S. Computer Engineering, May 2021, University of Notre Dame

B.S. Electrical Engineering, May 2021, University of Notre Dame

Publications

• S. Davis, Z. M. Enciso, L. Pei, and N. Cao, “Process Variation in Probabilistic Compute-in-Memory: Challenge and Opportunity,” 2026 IEEE 8th International Conference on Artificial Intelligence Circuits and Systems (AICAS), publication pending.
• Z. M. Enciso, X. Niu, X. Wang, M. Sharifi, S. Mukherjee, L. Pei, H. Mulaosmanovic, S. Duenkel, S. Beyer, M. Niemier, K. Ni, and N. Cao, “A 185 TOPS/W/mm2 Bayesian Inference Engine with 640 aJ, Write-Free FeFET GRNG for Uncertainty-Aware Aerial Search and Rescue,” IEEE Transactions on Circuits and Systems for Artificial Intelligence, publication pending.
• S. S. Wong, C. C. Tamarit, M. Sharifi, Z. M. Enciso, D. Reis, and M. Niemier, “Increasing the Efficiency of Associative Processor Architectures via CMOS-Compatible Hybridization,” 2026 Design, Automation & Test in Europe Conference (DATE), Verona, Italy, 2026, pp. 1-7, doi: 10.23919/DATE69613.2026.11539066.
• Z. E. Michaels, Tactical Edge: Accelerating Trusted, Autonomous AI for Safety-Critical, Resource-Constrained Systems, PhD Dissertation, University of Notre Dame, 2026, doi: 10.7274/31968741.
• Z. M. Enciso, J. Liu, B. Cheng, L. Pei, S. Davis, Y. Qin, Z. Jia, X. Hu, Y. Shi, M. Niemier, and N. Cao, “A 350 pW Implantable Ventricular Arrhythmia Detection Engine with Bayesian Uncertainty Quantification in 65 nm CMOS,” IEEE Journal of Solid State Circuits (Early Access), doi: 10.1109/JSSC.2026.3669040.
• Z. M. Enciso, X. Hu, N. Cao, K. Ni, and M. Niemier, “Unmasking Peripheral Circuit Overheads in Compute-in-Memory Macros with Emerging Memory Technology,” 2025 Semiconductor Research Corporation TECHCON, Austin, TX, USA, 2025.
• L. Pei, Y. Qin, Z. Enciso et al, “Towards Uncertainty-Quantifiable Biomedical Intelligence: Mixed-signal Compute-in-Entropy for Bayesian Neural Networks,” 2024 International Conference on Computer-Aided Design (ICCAD), New York, NY, USA, 2025, pp. 1-9, doi: 10.1145/3676536.3676806.
• J. Liu, L. Pei, Z. M. Enciso, B. Cheng, S. Davis, and N. Cao, “A 65 nm Uncertainty-quantifiable Ventricular Arrhythmia Detection Engine with 1.75 μJ per Inference,” 2025 International Solid-State Circuit Conference, San Francisco, CA, USA, 2025, pp. 1-3, doi: 10.1109/ISSCC49661.2025.10904610.
• B. Cheng, J. Liu, S. Davis, Z. M. Enciso, and N. Cao, “A 65 nm Neuromorphic Bio-Signal Encoder with Compute-in-Entropy Architecture 7.13 nJ Privacy-Preserving Encoding and 2.38 Mb/mm2 Item Memory Density,” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631333.
• B. Cheng, J. Liu, S. Davis, Z. M. Enciso, Y. Zhang, and N. Cao, “VAE-HDC: Efficient and Secure Hyper-Dimensional Encoder Leveraging Variation Analog Entropy,” Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), New York, NY, USA, 2024, art. 307, doi: 10.1145/3649329.3658486.
• J. Liu, B. Chang, Z. Enciso, S. Davis and N. Cao, “CIPUF: Towards On-chip Learnable Anomaly Detection with Compute-In-PUF Architecture,” 2024 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), New York, USA, 2024, pp. 1-6, doi: 10.1145/3665314.3670797.
• M. Niemier, Z. Enciso, M. M. Sharif, X. S. Hu, I. O’Connor, and A. Graening, “Smoothing Disruption Across the Stack: Tales of Memory, Heterogeneity, & Compilers,” 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-10, doi: 10.23919/DATE58400.2024.10546772.
• M. S. Islam, Z. Enciso et al, “A 0.57 mm2 Platform with 70.7% Efficient 4 mA 3.2 V Charge Pump and a Current-Input Ramp ADC for Implantable Optical Sensing of Tumors,” 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS), Toronto, ON, Canada, 2023, pp. 1-5, doi: 10.1109/BioCAS58349.2023.10389076.
• S. Dutta, B. Grisafe, C. Frentzel, Z. Enciso et al., “Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security,” IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 516-522, Feb. 2021, doi: 10.1109/TED.2020.3045380.
• Z. M. Enciso, S. Hadi Mirfarshbafan, O. Castañeda, C. J. Schaefer, C. Studer and S. Joshi, “Analog vs. Digital Spatial Transforms: A Throughput, Power, and Area Comparison,” 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA, USA, 2020, pp. 125-128, doi: 10.1109/MWSCAS48704.2020.9184566.

Experience

University of Notre Dame, Visiting Researcher

• May 2026–Present

University of Notre Dame, Graduate Research Assistant

• July 2021–April 2026
• Coincided with tenure as a Semicondunctor Research Corporation (SRC) Rearch Scholar (October 2021–April 2026) and as a National Defense Science and Engineering Graduate Fellow (NDSEG) (September 2022–September 2025)

Intel Corporation, Technology Development Intern

• May 2019–August 2019
• I developed an integrated, Internet of Things (IoT) hardware platform to address inefficiencies within manufacturing. In addition, I applied the principles of Lean Six Sigma to drive improvement of factory, automation, materials and labor systems to optimize manufacturing performance.

Honors/Awards

• National Defense Science and Engineering Graduate Fellow
• Design Automation Conference Young Fellow
• Jack and Mary Ann Remick Fellowship in Engineering
• Sigma Xi, The Scientific Research Honors Society
• IEEE Eta Kappa Nu Honors Society
• ACM Upsilon Pi Epsilon Honors Society
• University of Notre Dame College of Engineering Dean’s List

Skills

• Mixed-signal integrated circuit design in bulk CMOS+FeFET, FDSOI, and FinFET
• Mismatch-tolerant, arrayed circuit layout
• Hyperscale, parasitic-annotated circuit simulation
• Analog design flow with Cadence Virtuoso & Siemens Calibre, digital design flow with Cadence Genus
• PCB design for prototype validation
• Linux system administration & shell scripting
• Data analysis and visualization (Python)
• High-performance modeling (Rust)

Fabricated Prototypes

Bayesian Inference Accelerator with In-Word Gaussian GRNG (See publications)

Bayesian neural networks can quantify the certainty of their decisions, offering a degree of trust for machine learning-enabled, safety critical applications. I led the design of a CMOS Bayesian accelerator that targets the significant computational overhead associated with Gaussian random number generation (GRNG) with a novel, in-word GRNG circuit. This chip, validated in 65 nm CMOS, leverages fully analog compute-in-memory (CIM) to remove the need for digitizing entropy. It also features several algorithmic optimizations, like weight decomposition, selective Bayesian layers, and heterogeneous quantization. The resulting accelerator is suitable for deployment on SwaPC-constrained systems and demonstrates improvements in BNN inference energy efficiency over state-of-the-art accelerators. Future iterations will explore using emerging devices for GRNG and computation.

FeFET-Based Compute-in-Memory Accelerator for Machine Learning

I led the design of a CIM accelerator with a ferroelectric FET (FeFET) nonvolatile memory (NVM) that overcomes some of the traditional bottlenecks of such systems. Firstly, in recognition of the power and area domination by peripheral circuitry, this chip features a novel, CIM-customized, 8-bit SAR ADC design that can be pitch-matched to the CIM array columns. This removes the need for time-multiplexing several columns with a single ADC, greatly increasing the array throughput. In addition, this chip utilizes buffered, time-domain DACs to increase input data throughput—another common bottleneck.

Bio-Compatible Sensing Chip (See Publications)

I aided in the design of an injectable chip for imaging cancer cells. The chip is equipped with two vertical-cavity surface-emitting lasers (VCSELs), which produce beams with different wavelengths for multi-spectral imaging. On-chip photodetectors measure the reflected light, and this data is digitized and transmitted off-chip. The primary constraint of any self-contained, injectable system is generally the volume it occupies. A standard 16-gauge hypodermic needle has an inner diameter of less than 1.3 mm, which precludes on-board batteries and limits the size of the antenna and other electronic components on-chip. Therefore, the chip was designed to be powered and operated completely wirelessly, with additional circuitry to rectify and subsequently boost the wireless power to drive the VCSELs.

CAO 16 June 2026. Return to duck-pond.org.